Codasip GmbH

About Codasip

Codasip is a European semiconductor design company that develops RISC-V processor IP (embedded and application cores) as well as the electronic design automation tool Codasip Studio. Rather than physical manufacturing, its value creation lies in processor architecture, verification through simulation and formal methods, and the customization of processor cores via the CodAL description model. The portfolio includes standardized RISC-V cores, CHERI-enabled security cores against memory-safety vulnerabilities, custom vector processing, and automotive-grade processors per ISO 26262 and ISO/SAE 21434; in October 2025 the RISC-V processors were certified up to ASIL-D. Target industries are regulated markets such as critical infrastructure, defense, and aerospace, automotive, industrial, IoT, as well as HPC and AI. Codasip was founded in 2014 after ten years of research at Brno University of Technology, employs around 250 staff (of whom 57% hardware and 30% software engineers), and is headquartered in Munich with design centers in Europe and offices in the USA and South Korea.

Site

München

Processes

RISC-V processor IP licensing (embedded and application cores), Codasip Studio (EDA tool for processor design and custom compute), CHERI-enabled secure RISC-V cores, Custom vector processing, Processor co-design / bounded customization, Simulation (including SIM-V integration), Verification (simulation and formal verification), Automotive-grade processors (ISO 26262, ISO/SAE 21434)

Materials

CodAL description language, CHERI security architecture, RISC-V ISA

Certificates

ASIL-D (ISO 26262, product-related)

Founded

2014 (acco

Employees

approx. 250

Industries

Semiconductors, Critical national infrastructure, Defense, avionics & aerospace, Automotive, Industrial, IoT

1. 01

   Processor architecture in CodAL

2. 02

   RTL and SDK generation with Codasip Studio

3. 03

   Bounded Customization / Custom Compute

4. 04

   Simulation (including SIM-V integration) and formal verification

5. 05

   Licensing of processor IP

Technologies & Processes

Locations

Products

Inside the production

Quality & Certification

The RISC-V processors are developed according to ISO 26262 and ISO/SAE 21434 and were certified up to ASIL-D in October 2025. Verification is performed through simulation (including MachineWare SIM-V) and formal methods.

History

1. 2004

   Karel Masařík begins his doctorate on hardware/software co-design, which becomes the core of Codasip Studio.

2. 2014

   Founding of Codasip after ten years of research at Brno University of Technology.

3. 2015

   Seed funding of USD 4.5 million from Credo Ventures.

4. 2017

   Co-founding of RISC-V International; first commercial RISC-V processor IP; first 64-bit RISC-V core.

5. 2018

   Series A of USD 10 million; joins the CHIPSAlliance; Vidtoo Technology licenses the Bk3 RISC-V core.

6. 2019

   EU Horizon 2020 funding; new strategic design center in France.

7. 2020

   100 employees reached.

8. 2021

   New design center in the United Kingdom; Ron Black becomes CEO.

9. 2022

   Design centers in Greece and Spain; acquisition of Cerberus (secure IoT products).

10. 2025

    RISC-V processors certified up to ASIL-D; accelerated sales process initiated; licensing agreement with EnSilica for a CHERI-enabled embedded CPU.

11. 2026

    Strategic pivot and divestiture announced.