Engineering services for digital and mixed-signal chip development: RTL, verification, FPGA and backend through to tapeout
semify GmbH
Graz, AustriaNew on Amplifa
About semify
semify GmbH is an Austrian engineering company headquartered in Graz, specialized in digital design and verification for semiconductor development. The team supports customers from architecture and specification through RTL implementation (SystemVerilog/Verilog, Lint, CDC/RDC) and functional verification with UVM to backend implementation with synthesis, DFT support, Place & Route, STA, gate-level simulation and ECO. Further focuses include mixed-signal ASIC development for power management, audio, NFC and MEMS, FPGA prototyping, the integration of RISC-V cores, as well as Edge-AI and embedded software development with TensorFlow Lite, PyTorch Mobile, C/C++ and Python. All engineers are based in Central Europe, enabling short communication lines and close collaboration. The company works on a project basis either fully integrated in customer teams or independently according to milestones, and serves major OEMs among others in automotive, AI/compute and power management.
- Site
- Graz, Austria
- Processes
- Digital Frontend Design & Verification (RTL, UVM, lint/CDC), FPGA Prototyping & Platform Bring-up, Digital Backend Implementation & Sign-off (Synthesis, DFT, Place & Route, STA, GLS, ECO), Mixed-Signal ASIC Design (Power Management, Audio, NFC, MEMS), SoC & Subsystem Verification (incl. Gate-Level Simulation), Edge AI/ML Model Development & Embedded Software (TensorFlow Lite, PyTorch Mobile, C/C++, Python), Post-Silicon Lab Support (Debug, Re-Simulation, ECO Implementation), Digital Frontend Design & Verification
- Materials
- Digital Frontend Design & Verification, Digital Backend Implementation & Sign-off, Mixed-Signal ASIC Design, FPGA Prototyping, SoC & Subsystem Verification, Edge-AI & Embedded Software, RISC-V Core Integration
- Certificates
- Milestone-based quality gates (Stone/Bronze/Silver/Gold)
- Founded
- 2020
- Industries
- Semiconductors, Automotive, Power Management, AI/Compute, Consumer Electronics
- 01
RFI, RFQ, RFP
- 02
Architecture & Specification
- 03
RTL Implementation
- 04
Functional Verification
- 05
FPGA Prototyping
- 06
Synthesis, DFT, Place & Route, STA
- 07
Gate-Level Simulation & Sign-off
- 08
Tapeout
- 09
Lab Support, Re-Simulation & ECO
Services & Methods
Digital Frontend Design & Verification
RTL implementation with SystemVerilog/Verilog, Lint, CDC/RDC as well as UVM environments, assertions and coverage closure.
Digital Backend Implementation & Sign-off
Synthesis, constraints, DFT support, Place & Route, STA and gate-level simulation through to tapeout.
Mixed-Signal ASIC Design
Digital development for mixed-signal ASICs in power management, audio, battery management, NFC and MEMS.
FPGA Prototyping
Prototype architecture, platform bring-up and reusable lab evaluation systems.
SoC & Subsystem Verification
Top-level and subsystem verification including dynamic CDC, formal verification and gate-level simulation.
Edge-AI & Embedded Software
Development of energy-efficient neural network accelerators and embedded software with TensorFlow Lite and PyTorch Mobile.
RISC-V Core Integration
Integration and adaptation of open-source RISC-V cores such as CVA6 and Ibex into SoC environments with interconnects and peripherals.
Locations
Graz
ATHeadquarters and Engineering
- Materials
- Digital & Mixed-Signal Design, Verification, FPGA, Edge AI
- Open-source and commercial EDA toolchains
- FPGA prototyping platforms
- Verification environments (UVM)
Projects & Application Areas
Inside the production
Industries
Processes & technical limits
| Processes | Tolerance | Max. part | Weight | Lot size | Materials |
|---|---|---|---|---|---|
| Digital Frontend Design & Verification (RTL, UVM, lint/CDC)Engineering | – | – | – | – | – |
| FPGA Prototyping & Platform Bring-upEngineering | – | – | – | – | – |
| Digital Backend Implementation & Sign-off (Synthesis, DFT, Place & Route, STA, GLS, ECO)Engineering | – | – | – | – | – |
| Mixed-Signal ASIC Design (Power Management, Audio, NFC, MEMS)Engineering | – | – | – | – | – |
| SoC & Subsystem Verification (incl. Gate-Level Simulation)Engineering | – | – | – | – | – |
| Edge AI/ML Model Development & Embedded Software (TensorFlow Lite, PyTorch Mobile, C/C++, Python)Engineering | – | – | – | – | – |
| Post-Silicon Lab Support (Debug, Re-Simulation, ECO Implementation)Engineering | – | – | – | – | – |
Additional services
Reference customers
Quality & Working Method
semify works with defined milestones and quality gates along the entire project process, from architecture through static design checks and verification closure to sign-off. Lab support, re-simulation and ECO implementation accompany the projects beyond tapeout.
| Evidence | Graz |
|---|---|
| Milestone-based quality gates (Stone/Bronze/Silver/Gold) |
History
- 2020
Founded in Graz by DI Klaus Strohmayer