Synogate designs digital circuits for FPGAs and ASICs using tools and methods from software development.
Synogate UG (haftungsbeschränkt)
BerlinNew on Amplifa
About Synogate
Synogate is a deep-tech company founded in Berlin in 2021 that develops custom digital circuits for FPGAs and ASICs. The team specializes in RTL design and implements complex algorithms as high-performance hardware solutions, among other things using its own open-source hardware construction library Gatery. The service portfolio includes RTL design services, FPGA implementation and verification, hardware-software co-design, embedded software development for RISC-V, PCB design, network offloading, LLM acceleration, as well as development and licensing of IP cores such as HashCache, a key-value store for high-performance stateful networking. In the field of network resilience testing, Synogate generates 400 GbE and more of attack traffic for DDoS tests with a single device. The company's hardware-implemented cybersecurity components have been audited by the German Federal Office for Information Security (BSI) and are in use by the German government. In 2022, Synogate was funded by the StartUpSecure grant of the BMBF; the founding was supported in 2021 under the EXIST program by the BMWi and the European Social Fund. Customers come from network technology, semiconductor design, data centers, high-performance computing, financial trading, cryptography and AI.
- Site
- Berlin
- Processes
- RTL design (custom digital circuits, VHDL 2008 / Verilog), FPGA implementation and verification, Hardware-software co-design, Embedded software development (RISC-V), PCB design for compact systems, Network resilience testing (400 GbE attack traffic with a single device), Network offloading (hardware acceleration of network tasks), LLM acceleration (FPGA-based accelerator for LLM inference)
- Materials
- FPGA Implementation, ASIC Design, RTL Design (VHDL 2008/Verilog), IP Core Development & Licensing, Hardware-Software Co-Design, Embedded Software (RISC-V), PCB Design, Network Offloading & Resilience Testing
- Certificates
- BSI audit (cybersecurity components), ISO 9001
- Founded
- 2021
- Industries
- Network Technology/Cybersecurity, Semiconductor/Chip Design, Data Centers/Cloud, High-Performance Computing, Financial Trading, Cryptography
- 01
Requirements analysis & consulting
- 02
RTL design (C++/Gatery, VHDL 2008/Verilog)
- 03
Simulation, unit tests & fuzzing
- 04
FPGA implementation & verification
- 05
HW-SW integration & PCB design
- 06
Documentation, generators & licensing
Technologies & Methods
FPGA Implementation
Realization of digital circuits on platforms such as AMD Xilinx UltraScale+, Intel Altera Agilex 7/Stratix 10, Lattice ECP5 and GateMate.
ASIC Design
Implementation of logic as application-specific integrated circuits.
RTL Design (VHDL 2008/Verilog)
Custom digital circuits, among other things using the company's own open-source library Gatery with generatable, synthesizable VHDL-2008 output.
IP Core Development & Licensing
Configurable IP cores including generators, testbenches and interface documentation, e.g. HashCache and Gatery-based components.
Hardware-Software Co-Design
Integration of hardware and software including drivers, protocols (UART, SPI, I2C, AXI, USB, HDMI) and legacy system integration.
Embedded Software (RISC-V)
Embedded software development including RISC-V processors implemented on FPGAs.
PCB Design
Board design for compact systems with limited installation space and power budget.
Network Offloading & Resilience Testing
Hardware acceleration of network tasks as well as DDoS test traffic with 400 GbE and more from a single device.
LLM Acceleration
FPGA-based accelerator for LLM inference with optimized memory access patterns.
Locations
Berlin
DEHeadquarters, Development & Design
- Lot size
- Prototype to single projects
- Materials
- RTL design, FPGA, ASIC, IP cores, embedded software, PCB design
- FPGA development platforms (AMD Xilinx, Intel Altera, Lattice, GateMate)
- In-house simulation environment
- Network test hardware up to 400 GbE
IP Cores & Solutions
Inside the production
Industries
Processes & technical limits
| Processes | Tolerance | Max. part | Weight | Lot size | Materials |
|---|---|---|---|---|---|
| RTL design (custom digital circuits, VHDL 2008 / Verilog)Engineering | – | – | – | – | – |
| FPGA implementation and verificationEngineering | – | – | – | – | – |
| Hardware-software co-designEngineering | – | – | – | – | – |
| Embedded software development (RISC-V)Engineering | – | – | – | – | – |
| PCB design for compact systemsEngineering | – | – | – | – | – |
| Network resilience testing (400 GbE attack traffic with a single device)Testing | – | – | – | – | – |
| Network offloading (hardware acceleration of network tasks)Engineering | – | – | – | – | – |
| LLM acceleration (FPGA-based accelerator for LLM inference)Engineering | – | – | – | – | – |
| IP core generators (Gatery, C++-based hardware construction library)Engineering | – | – | – | – | – |
| HashCache IP core (key-value store, >60 million sessions/s insert, latency 0.2 µs on externalEngineering | – | – | – | – | – |
| Consulting (algorithms, machine learning, cryptography, network technologies,Engineering | – | – | – | – | – |
Additional services
Reference customers
Quality & Auditability
The auditability of the RTL code was demonstrated by the audit of hardware-implemented cybersecurity components by the German Federal Office for Information Security (BSI). Designs are verified through unit tests, testbenches and fuzzing tests across the entire design hierarchy.
| Evidence | Berlin |
|---|---|
| BSI audit (cybersecurity components) | |
| ISO 9001 |
History
- 2021
Founding with funding under the EXIST program by the BMWi and the European Social Fund
- 2022
StartUpSecure grant of the BMBF; patent application for HashCache filed