Develops air-cooled AI inference systems for datacenters, from chip to software integration
Tensordyne Inc.
Sunnyvale, CA (USA) · Munich (Germany)New on Amplifa
About Tensordyne
Tensordyne develops multimodal generative AI inference systems for datacenters, from a single rack to thousands of racks. The company designs the entire system stack in-house: logarithmic-math-based compute architectures (TDN Math), inference chips such as Scorpio and Napier, compute trays, the Scale-up Interconnect TDN Link, and software integration via PyTorch, Triton and vLLM under Kubernetes. The systems are fully air-cooled and can be deployed in existing datacenters at roughly 30 kW per pod without liquid cooling. Target industries are hyperscalers, Neo Clouds, enterprise on-premise installations, as well as application-layer companies and foundation model builders. The company operates as Tensordyne Inc. (Sunnyvale, California) and Tensordyne GmbH (Munich) with locations in North America and Europe. Chips are manufactured as a fabless company in partnership with Broadcom and TSMC; its own value creation lies in architecture, chip design, system and software development.
- Site
- Munich
- Processes
- AI inference systems for datacenters (rack up to thousands of racks), Air-cooled inference hardware (30 kW per pod), Software integration via PyTorch, Triton, vLLM / Kubernetes, Scale-up Interconnect (TDN Link), Support for MoE and agentic models
- Materials
- Log-Math Architecture, Inference Chips (Scorpio, Napier), Compute Tray, Scale-up Interconnect
- Certificates
- G2 Certification (IDCA SDS Evaluation)
- Industries
- Hyperscalers, Neo Clouds, Enterprise On-Prem AI, Application-Layer Companies, Foundation Model Builders
- 01
TDN Math (logarithmic compute architecture)
- 02
Chip design (TDN AIP, fabless with Broadcom/TSMC)
- 03
Compute tray development (TDN ACT)
- 04
Scale-up Interconnect (TDN Link)
- 05
System integration up to rack level
- 06
Software integration (PyTorch, Triton, vLLM, Kubernetes)
- 07
Support and fleet operations
Technologies & Components
Log-Math Architecture
Proprietary logarithmic compute approaches as the foundation for energy-efficient AI inference.
Inference Chips (Scorpio, Napier)
7nm (Scorpio) or 3nm silicon (Napier), manufactured at TSMC in partnership with Broadcom.
Compute Tray
System unit for housing the inference chips in a rack assembly.
Scale-up Interconnect
Any-to-any cell-based interconnect for linear scaling and low latency.
Locations
Sunnyvale, CA
USUS head office / Headquarters
Munich
DEGermany location (1st floor)
System Components
Inside the production
Industries
Additional services
Quality & Certification
In 2025, Tensordyne was awarded the G2 certification level by the International Data Center Authority (IDCA) upon completion of the SDS evaluation process. This confirms the system design, deployment discipline and service quality of the enterprise AI platform at datacenter scale.
| Evidence | Sunnyvale, CA | Munich |
|---|---|---|
| G2 Certification (IDCA SDS Evaluation) |
Company History
- 2019
First five foundational patents for Log-Math architectures filed; design of Scorpio (Gen-1 chip) begins
- 2021
Tape-out of Scorpio at Broadcom; functional 7nm silicon received from TSMC
- 2022
Functional Scorpio samples delivered to first validation customers
- 2023
Development of the Gen-2 architecture; focus on Transformer models and generative AI
- 2024
Strategic pivot to datacenter scale (Napier); technology partnership with Juniper Networks
- 2025
Optimization for MoE and agentic workloads; G2 certification by IDCA (September)
- 2026
3nm Napier chip tape-out (Broadcom/TSMC); transition to high-volume manufacturing at TSMC